With the progress of the digital technology in electric devices in recent years, demands for nonvolatile memory devices with a large capacity have been increasing for storing data such as music, images, information, and so on. As a measure to meet such demands, a non-volatile memory device (hereinafter referred to as ReRAM) has been attracting attention, which includes, as a memory cell, a variable resistance layer which has a resistance value that changes in response to a provided electric pulse and holds the state. This is because the ReRAM has characteristics that the structure as a memory cell is comparatively simple and suitable for increasing density, and that it is easy to ensure consistency with conventional semiconductor processes.
With such a ReRAM, a material which can stably cause a designed change in a resistance value with an excellent reproducibility even when a memory cell is miniaturized and establishment of a manufacturing process of the memory cell are required. Research and development for such a material and a manufacturing process are actively conducted.
A memory cell array having a stacking structure is proposed as a structure allowing further dense integration in the ReRAM.
FIG. 16 shows diagrams of a memory cell array having a conventional stacking structure, an enlarged view of a memory cell, and an equivalent circuit diagram of the memory cell, disclosed by Patent Literatures 1 and 2. The memory cell array includes: a stacked body in which a plurality of conductive layers (N-type polysilicon) 1511 and a plurality of interlayer insulating films 1512 are alternately stacked; a variable resistance layer 1515 formed to perpendicularly cross the stacked body and to have a cylindrical shape; a metal layer 1516 formed to be in contact with an inner periphery of the variable resistance layer 1515 and to have a cylindrical shape; a columnar electrode 1517 formed to be in contact with an inner periphery of the metal layer 1516 having the cylindrical shape; a P-type polysilicon layer 1513 interposed between the variable resistance layer 1515 having the cylindrical shape and the N-type polysilicon layer 1511 to be in contact with the N-type polysilicon layer 1511; and a metal silicide layer 1514 which is in contact with the P-type silicon layer 1513.
In one memory cell included in the memory cell array, a stacked body having the metal layer 1516, the variable resistance layer 1515, and the metal silicide layer 1514 serves as a variable resistance element, and a stacked body having the P-type polysilicon layer 1513 and the N-type polysilicon layer 1511 serves as a PN diode.
In addition, FIG. 17 shows a memory cell array having a conventional stacking structure disclosed by Patent Literature 3. The memory cell array includes: a stacked body in which a plurality of conductive layers 1611 and a plurality of interlayer insulating films 1612 are alternately stacked; a variable resistance layer 1613 formed to perpendicularly cross the stacked body and to have a cylindrical shape; a first semiconductor layer 1614 formed to be in contact with an inner periphery of the variable resistance layer 1613 and to have a cylindrical shape; a second semiconductor layer 1615 formed to be in contact with an inner periphery of the first semiconductor layer 1614 and to have a cylindrical shape; and a columnar electrode 1616 formed to be in contact with an inner periphery of the second semiconductor layer 1615.